Design and Verification
We primarily concentrated on improving the Design Verification abilities that the industry requires. The curriculum
is created with the most recent industry-adopted approaches. You will have practical expertise with Verilog design and
verification using System Verilog (SV) in UVM methodology by the end of the course.
In order to help future engineers become some of the best ASIC verification engineers in the VLSI verification industry,
our ASIC verification course provides them with intensive training on the most popular and cutting-edge verification approaches.
Course Content
- Introduction to VLSI
- VLSI Design Flow
- Introduction to Digital Electronics
- Universal Logic Elements
- Combinational Circuits - Design and Analysis
- Arithmetic Circuits
- Data processing Circuits
- Sequential Circuits - Design and Analysis
- Latches and Flip flops
- Shift Registers and Counters
- Memories – ROM and RAM
- Finite State Machine & Sequence detection
- Introduction To HDL
- Design methodology
- Logical operators
- Data types
- System tasks
- Compiler directives
- Gate level modeling
- Data flow modeling
- Behavioral modeling
- Blocking and Non-Blocking assignments
- Time scale precession
- Loops
- Conditional statements
- Delays
- Tasks and functions
- Finite State Machine
- System Verilog Vs Verilog
- Data Types
- Arrays
- Procedural Statements and Control Flow
- Processes threads
- Tasks and Functions
- Classes
- Randomization
- Constraints
- IPC
- Assertions
- Coverage
- Verification process and Testbench
- UVM hierarchy
- Sequence item
- Sequence
- Sequencer
- Driver Sequencer Handshake
- Driver
- Config DB
- Agent
- Phases
- Monitor
- Scoreboard
- Environment
- Test
- Top
- TLM Ports
- RAL