Design for Testability
Design for Testability (DFT) in SOC Design flow looks for manufacturing flaws in designs. Over time, DFT has developed into a
distinct speciality due to the evolution of manufacturing processes and the resulting growth in size and complexity of chips.
DFT Engineers strive to make logic, memory, and interconnects more testable by incorporating a variety of test structures into
the design flow.
Our DFT training program includes numerous hands-on projects based on SCAN, ATPG, JTAG, and MBIST and is designed to meet the
needs of the modern industry.
Course Content
- Introduction to DFT
- Roles in DFT
- Full SOC flow – DFT
- DFT Architecture and Basics
- Test Plan
- Different DFT schemes
- Comparison between Functional and DFT Vectors
- Defect, Fault and Error
- Understanding of SCAN Insertion
- Scan methodology
- Types of scan
- Top – down and Bottom-up Approach
- Scan Insertion flow
- Scan operation
- Clock structure relation in SCAN
- DFT rule checks – Clock and Reset
- Mutiple Clock domains
- Precautions for building a proper scan chain
- Edge and Domain mixing significance
- Scan configurations
- Scan chain balancing
- Lock up and terminal lockup latches
- ATPG Tools introduction
- Fault models
- Fault categories
- Algorithms used in ATPG
- ATPG flow
- Coverage Analysis
- Fault Classes
- ATPG DRC’s
- Hand on Struck-at ATPG
- Concepts related to STA – Basics
- MCP and FP
- Transition Delay faults
- Transition Delay faults
- Introduction to compression
- Compression architecture
- Decompressor and Compactor
- LFSR
- Compression ratio
- Masking logic
- One hot decoder
- Modular compression
- Types of patterns
- Formats of patterns
- Fault grading
- LOC, LOS and LOES
- On chip clock control
- Advantages
- Disadvantages
- Internal structure
- Introduction to validation
- Simulations flow
- Simulation mismatches debug
- No timing and Timing based simulations
- Flat models
- Introduction to JTAG/ IJTAG
- Introduction to PADS
- BS insertion
- JTAG/ IJTAG FSM
- Instructions of JTAG/ IJTAG
- Introduction to MBIST
- Memory faults
- Memory grouping
- Memory basics
- Algorithms
- MBIST insertion on RTL