Physical Design
Giving students a comprehensive hands-on experience in Physical design and Physical verification using the newest tools and
extensive lab practice was the main aim of the Physical Design Training course. You will get the ability to operate in a Linux
environment, comprehend the entire physical design pipeline, including Partitioning, Floorplanning, Powerplanning, Timing analysis,
Clock tree synthesis, Routing, Physical verification and Sign-off checks by the end of the course.
To deliver a chip on schedule and with perfect design, you need to be proactive, have thorough analysis and understanding,
have a track record of success, and have faultless design. We teach exactly these fundamentals in our renowned physical design training.
Course Content
- CMOS fundamentals
- Basic logic using CMOS
- Fabrication Process
- Key terminologies
- Photolithography
- Etching
- Limitations in Fab to manufacture lower technology nodes
- Basic Gates
- Combinational Logic
- Adder
- Subtractor
- Encoder & Decoder
- Muxes & Demuxes
- K-map Optimization
- Sequential Logic
- Equations/ Characterization tables
- Counters
- Flip Flops
- Divider Circuits
- Finite State Machine Design
- Introduction and Working knowledge of UNIX/LINUX commands
- File handling skills in UNIX/LINUX
- GVIM – major shortcuts
- Text processing commands
- FPGA Design Flow
- Full Custom Design flow (Analog)
- Semi-Custom Design flow (Digital)
- Need for HDL
- Characteristics of Verilog HDL
- Methods of modelling
- Modelling of combinational logic circuits
- Modelling of sequential logic circuits
- What is Synthesis
- Inputs and Outputs of Synthesis
- Basic Synthesis flow
- Wire Load Models
- Non-Linear Delay Models
- Optimization techniques
- Scan Insertion
- Fundamentals of STA
- Role of STA in the design flow
- Pre Layout STA & Post Layout STA
- Basic terminologies in STA
- Timing paths
- Timing Exceptions
- Timing checks and Analyzing reports
- Fixing Setup and Hold violations
- PD flow
- Basic PD terminologies
- Floorplan
- Guidelines
- Design Setup
- Macro placement guidelines
- Powerplan
- Creation of Rings
- Creation of Power stripes
- Creation of PG rails
- Placement
- Physical Cells
- Placement strategies
- Placement Steps
- Congestion Analysis
- Timing Analysis
- Congestion vs Timing
- Clock Tree Synthesis
- Basics of CTS
- Approaches to CTS
- Clock Exceptions
- Clock skew balancing
- Clock net routing
- Non Default routing
- Analyzing clock trees
- Clock Tree Optimization
- Useful clock skew
- Clock cloning
- Clock Concurrent optimization
- CTS impact on placement or power
- Timing Analysis
- Routing
- Routing flow
- Global Routing
- Track Assignment
- Detailed Routing
- Search and Repair
- Timing Analysis
- Antenna effect
- Metal filling
- Latchup
- Dishing effect
- Metal Slotting
- Derates
- CRPR
- OCV
- AOCV
- POCV
- Double Patterning Technology
- Signal Integrity
- Crosstalk & Noise analysis
- IR Drop Analysis
- ECO